Digital-GrandTest1-Q14

+3 votes

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asked Jun 19 in Digital by gbmentor (85,520 points)
reshown Jun 20 by gbmentor

4 Answers

+2 votes
 
Best answer

 

Q0 Q1 Q2 Q3 Q0(new)=Q0' Q1(new)=Q1' Q2(new)=Q0Q1 Q3(new)=Q0Q1(xor)Q2
0 0 0 0 1 1 0 0
1 1 0 0 0 0 1 1

Clear input becomes 1 here. Counter reset.

(check comment for clear)

Mod=2 

But my doubt is as this is a synchronous counter and CLK edge is required along with CLR=0 to clear then why we are not considering this as MOD-3 counter ???

@getgatebook

answered Jun 20 by tskushagra-guptacse (15,900 points)
edited Jun 21 by gbmentor
when the counter is at 1100 state. During the clock trigger, the clear input becomes 1. and the counter is reset to 0000. i.e 0011 is not reached as a stable state.
Hence only 2 states.
0000 & 1100.
Hence mod 2.
http://thegatebook.in/qa/4047
Sir can you clear my query related to this question also?
(Second last comment)
0 votes
Mod 2 so 4 is correct one
answered Jun 20 by tsnikhilsharmagate2018 (30,630 points)
+1 vote

N=2 so 2^2 =4 is correct one.

answered Jun 20 by tsnikhilsharmagate2018 (30,630 points)
Can we not do this question directly by seeing which input is making the counters clear. But the same confusion of LSB and MSB exist?
0 votes
I am getting mod 3 counter. Hence, answer =8
answered Jun 20 by tssharmaayush361 (420 points)
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