# Digital-GrandTest1-Q13

A 3 bit down counter is used to control the output of multiplexer as shown in the figure. The counter is initially at $(101)_2$ the output of multiplexer will follow the sequence:

$(A). I_2, 0, I_1, 0.....$

$(B).I_1, 0, I_2, 0.....$

$(C).I_1, 0, 0, I_2......$

$(D).I_1, I_1, I_2, 0.....$

reshown Jun 20

+1 vote

Solution :

When E=0 , Mux is not enabled. Hence Output =0.

When E=1, Corresponding lines are selected.

Now since counter is a down counter starting at (101). Next sequence will be : (100) , (011) , (010) , (011)....so on

For example , when initially counter is 101: Select lines get S0=1, S1=0. Since S1 is msb. Line 1 is selected.

i.e Output will be I2.

Similarly the sequence will be I2,0,I1,0.
answered Jun 21 by (73,870 points)
–1 vote
B is correct one
answered Jun 20 by (24,690 points)
–1 vote

b is correct one.

answered Jun 20 by (24,690 points)
How you are deciding whether S0 is MSB and S1 is LSB?
If nothing is given than we always used left hand side man right hand side lsb
NO..S0 is always lsb, S1 is msb. unless said
Okk bro thanks
+1 vote
answered Jun 20 by (1,800 points)
Answer is A as S0 is lsb S1 as msb
Yes when lsb msb change than answer is b but a is correct because S1S0
MSB LSB

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So And is A

answered Jun 20 by (210 points)